RelMicroS IPs empower customers with the cutting edge solution they need to deliver reliable microelectronic systems characterized with high-efficiency, high-performance, and low-power designs for the leading-edge nodes.
RelMicroS IP Portfolio
1. Processor Core IP
RelMicroS provides a reliable RISC-V based Processor Core: RelCore. Based on the 64-bit RISC-V instruction set, RelCore is designed for ASIC and FPGA implementations.
RelCore supports an IEEE 754-2008-compliant floating-point unit. RelCore supports modern operating systems.
Design for Reliability
Intensive scaling for VLSI circuits is a key factor for gaining outstanding performance. However, this scaling has huge negative impact on the circuit reliability. As it increases the undesired effect of degradation and decreases the robustness of ultradeep submicrometer technologies operating in harsh environments.
RelMicroS is challenging this negative impact of scaling process, as RelMicroS uses state-of-the-art design techniques to provide fault tolerance designs, believing that creativity, efficiency, and performance are worthless if they are not served with an equal amount of reliability.
- Synthesizable Verilog RTL (.v).
- Verilog gate-level netlist (.v).
- GDSII layout (.gds).
- Footprint abstract (.lef).
- Timing model (.lib).
- Physical verification reports: DRC / LVS / ERC / ESD / ANT.
- Synthesis scripts (.tcl).
- Datasheet with integration guidelines (.pdf).